Data signals are frequently nowadays transmitted along optical fiber links. Most of the noise in such signals is exhibited as phase jitter, being created by dispersion within the fibers, differential slew rates in the edges of the signals caused by LED switching, and because of noise in transimpedance amplifiers. An international standard, FDDI, has been set requiring that data be transmitted at a set rate, typically 125MBs.sup.-1 in 4B/5B format (a five bit code word represents four data bits) and in non return to zero inverse (NRZ1) coding wherein a positive or negative transition in a bit period indicates a `1` and the absence of a transition in a bit period indicates a `0`. Transitions may occur at a maximum rate of one every bit period, and at a minimum rate of one every 10 bit periods (known as the master line state).
Thus a major problem in the design of receiver circuits for such data signals is the provision of a local clock which can accurately lock onto the incoming data signal despite phase jitter so that the data signal can accurately be decoded with minimal bit error rates.
In U.S. Pat. No. 4,806,880, assigned to Plessey Overseas Limited there is disclosed a receiver circuit including a modified Costas phase locked loop including a voltage controlled oscillator (herein referred to as a VCO) and dual integrate and hold circuits responsive to an incoming biphase Manchester coded signal to provide an error signal to the VCO dependent on the phase difference between the incoming signal and a local clock signal. The dual integrate and hold circuits operate in phase opposition so that one circuit integrates for half a cycle while the other circuit holds and then resets. This type of operation is suitable where there is a regular transition in each bit period providing phase information. However such circuits are not suitable where, as with NRZ1 coding, there is not a regular transition within the bit period of the incoming data signal, since transitions only occur when a `1` bit is indicated.